Multi/many core architecture is a natural form of utilizing
ever-increasing transistor count on a chip under the power budget
constraint. Now it is available for wide range of platforms,
from smartphones to servers in a huge data center.
However, just increasing the number of threads and splitting
the data strictures into smaller pieces could not only
underutilize the cores, but also lead to performance
degradation and/or wasted power consumption.
While techniques and methodologies of traditional parallel
programming are still useful, other factors need to be taken
into consideration for the current and future multi/many
core architecture, such as the characteristics of on-chip
integration, power budget constraint and the behavior of
new type application workload and usage models.
This special session is aimed to attract the interests
of people working in various aspects of multi/many core
architecture, from the circuit level to the application level,
stimulate the discussion and share and exchange their experiences
Topics of interests for the special session include
(but not limited to):
Performance and power-efficiency optimization,
Heterogeneous multi/many core: architectural design
and run-time support,
Parallelization libraries and tools,
Performance and power consumption modeling methodologies,
Design strategies for performance and power-efficiency in
circuit, architecture and software levels,
On-chip interconnect: architecture, protocol and routing,
Memory hierarchy architecture and protocol.
Last level cache (LLC) and memory bandwidth sharing effects.
5/15: Title and abstract submission
(sent to p2m2ca at oslab.biz by email)
6/1: Full paper submission
Paper Upload page of ISIC 2014)