Performance and Power Issues in Multi/Many Core Architecture

A special session at ISIC 2014 held in Singapore in December 2014.
Venue: Marina Bay Sands – Sands Expo and Convention Centre, Room 4102.
Date and Time: December 12, 2014, from 1330 to 1500.
Program: Session Program

Multi/many core architecture is a natural form of utilizing ever-increasing transistor count on a chip under the power budget constraint. Now it is available for wide range of platforms, from smartphones to servers in a huge data center.

However, just increasing the number of threads and splitting the data strictures into smaller pieces could not only underutilize the cores, but also lead to performance degradation and/or wasted power consumption.

While techniques and methodologies of traditional parallel programming are still useful, other factors need to be taken into consideration for the current and future multi/many core architecture, such as the characteristics of on-chip integration, power budget constraint and the behavior of new type application workload and usage models.

This special session is aimed to attract the interests of people working in various aspects of multi/many core architecture, from the circuit level to the application level, stimulate the discussion and share and exchange their experiences and knowledge.

Topics of interests for the special session include (but not limited to):

Important Dates


For more information, please refer to the following pages: or, send email to p2m2ca at .
International Symposium on Integrated Circuits (ISIC) 2014 Computer Architecture and Operating Systems group